1. Technical Field
This disclosure relates generally to circuit design properties, and more particularly to ranking of circuit design properties.
2. Description of the Related Art
As the complexity in circuit design has increased, there has been a corresponding improvement in various kinds of verification and debugging techniques. In fact, these verification and debugging techniques have evolved from relatively simple transistor circuit-level simulation (in the early 1970s) to logic gate-level simulation (in the late 1980s) to the current art that uses Register Transfer Language (RTL)-level simulation, and formal verification. RTL describes the registers of a computer or digital electronic system and the way in which data are transferred among the combinational logic between registers.
During some of these verification techniques, a circuit design may be tested against a set of properties to evaluate the operation of the circuit design. Properties are statements or expressions about some expected behavior of the circuit design. Some properties can be shown to be true or false during verification testing. Properties can be manually created by a circuit designer that examines the circuit design and manually codes the properties based on the circuit designer's own knowledge of the circuit design. Other tools may automatically generate circuit design properties to expedite the verification of the circuit design.
Tools that automatically generate circuit design properties are often over-inclusive and generate a large number of properties. Presenting all of these properties to the circuit designer with no additional information is overwhelming to the circuit designer. Additionally, property verification is a computationally intensive task and some of the automatically generated properties may be redundant or of little use in testing the circuit design. Thus, testing the circuit design against all of these properties would waste valuable computing resources and extend the time needed to verify a circuit design.